Static Random Access Memory (SRAM) constitutes a large portion of modern microprocessor designs. Stand alone SRAM chips also constitute a significant market. SRAM cell failures are a major consideration in all SRAM designs. Due to the fact that all cells in a given SRAM chip must function properly, the maximum operating speed and the minimum operating voltage of the SRAM chip are determined by the poorest performing or weakest cell. SRAM chips are extensively tested and failing cells are replaced when necessary and possible via various redundancy schemes. Once an SRAM chip has been qualified to be “good,” potential future cell failures may still exist. Such potential cell failures may be radiation-induced, pattern-dependent that escaped the standard testing, aging effects, or switching history effects in the case of partially depleted silicon on insulator (PDSOI) technology.
Pattern dependent fails may involve interaction among a number of cells in a local area switching in some particular worst case sequence. The circuit behavior in these situations depends on the amplitude of the cell power supply voltage as well as the amplitude of the signals that write and read the cells. In the case of PDSOI technology there are also floating body related effects that depend on the previous switching history that can lead to SRAM cell fails. For example, the stability of an SRAM cell against erroneous change of state during a read operation is a function of how long it has been since the cell was written. The worst case is a read immediately following a write. The situation improves as the write to read time increases up to about 10-100 μs, after which it becomes time independent. It is important to be able to characterize such behavior on a regular basis.
Such a characterization may be achieved by measuring the minimum operating power supply voltage (Vmin) of one or more cells as a function of the time delay between write and read. It is also of value to be able to characterize the intrinsic write and read times of memory cells as a function of various bias voltages. It is important to appreciate that while the absolute values of such voltages and times will vary from cell to cell, their dependencies on bias conditions represents a common behavior that can be understood and tracked by measuring just a small number of cells. In principal such behavior can be measured as high speed bench tests of the appropriately designed test structures. In practice this is seldom or never done and instead the nature of these effects is inferred from direct current (DC) or alternating current (AC) measurements on a large (>1 Mb) SRAM array, with a considerable degree of ambiguity, often augmented with basic DC current-voltage characterization of a few cells.
Thus, a need exists for test structures that may be used to efficiently measure such effects under high speed conditions, on a regular basis, with standard inline test equipment using only DC inputs and outputs.